/**
  @page TIM_Synchronization_Mode TIM Synchronization mode example
  
  @verbatim
  ******************** (C) COPYRIGHT 2014 STMicroelectronics *******************
  * @file    TIM/TIM_SynchronizationMode/readme.txt 
  * @author  MCD Application Team
  * @version V1.4.0
  * @date    24-July-2014
  * @brief   Description of the TIM Synchronization mode example.
  ******************************************************************************
  *
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  * You may not use this file except in compliance with the License.
  * You may obtain a copy of the License at:
  *
  *        http://www.st.com/software_license_agreement_liberty_v2
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
   @endverbatim

@par Example Description 

This example shows how to synchronize TIM peripherals in cascade mode, two timers
TIM2 and TIM3 are used.

Timers synchronisation in cascade mode:

 - TIM2 is configured as Master Timer:
     - PWM Mode is used
     - The TIM2 Update event is used as Trigger Output

 - TIM3 is slave for TIM2
     - PWM Mode is used
     - The ITR1(TIM2) is used as input trigger 
     - Gated mode is used, so start and stop of slave counter are controlled by
       the Master trigger output signal(TIM2 update event).

The TIM2 counter clock is 48 MHz.

  The TIM2 is running at:
  TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 187.5 KHz 
  and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.

  The slave Timer TIM3 is running at TIM2 clock:
  (TIM2 frequency)/ (TIM3 period + 1) = 46.87 KHz and a duty cycle equal 
  to TIM3_CCR1/(TIM3_ARR + 1) = 25%



@par Directory contents 

  - TIM/TIM_SynchronizationMode/stm32f0xx_conf.h    Library Configuration file
  - TIM/TIM_SynchronizationMode/stm32f0xx_it.c      Interrupt handlers
  - TIM/TIM_SynchronizationMode/stm32f0xx_it.h      Interrupt handlers header file
  - TIM/TIM_SynchronizationMode/main.c              Main program
  - TIM/TIM_SynchronizationMode/main.h              Header for main.c module
  - TIM/TIM_SynchronizationMode/system_stm32f0xx.c  STM32F0xx system source file
  
@note The "system_stm32f0xx.c" is generated by an automatic clock configuration 
      tool and can be easily customized to meet user application requirements. 
      To select different clock setup, use the "STM32F0xx_Clock_Configuration_VX.Y.Z.xls" 
      provided with the AN4055 package available on <a href="http://www.st.com/internet/mcu/class/1734.jsp">  ST Microcontrollers </a>

         
@par Hardware and Software environment

  - This example runs on STM32F0xx devices.
  
  - This example has been tested with STMicroelectronics STM320518-EVAL and
    STM32072B-EVAL including respectively STM32F051R8T6 and STM32F072VBT6 devices
    and can be easily tailored to any other supported device and development board

  - STM320518-EVAL Set-up
     - Connect the following pins to an oscilloscope to monitor the different 
      waveforms:
        - TIM2 CH1 (PA.05) 
        - TIM3 CH1 (PB.04)
  - STM32072B-EVAL Set-up
     - Connect the following pins to an oscilloscope to monitor the different 
      waveforms:
        - TIM2 CH1 (PA.05) 
        - TIM3 CH1 (PB.04)


@par How to use it ? 

In order to make the program work, you must do the following :
 - Copy all source files from this example folder to the template folder under
   Project\STM32F0xx_StdPeriph_Templates
 - Open your preferred toolchain 
 - Select the appropriate workspace 
 - Rebuild all files and load your image into target memory
 - Run the example

 * <h3><center>&copy; COPYRIGHT STMicroelectronics</center></h3>
 */
